The present invention relates to a transistor circuit using a MOS transistor, and particularly to a transistor circuit that can reduce leakage current and the like of the circuit in a standby state and thereby reduce power consumption.
Conventionally, LSI (integrated circuit) has a state in which only signal processing operation of the LSI is stopped while power is applied to the LSI, that is, a standby state.
For example, there is a product designed to temporarily stop operation until a time set by a timer and begin reproducing music or the like at the set time. A supply voltage is applied to the entire circuit of such a product at all times. While the product is in the standby state, only part of its circuit components such as the timer are in an operating state and the other circuit components forming most of the circuit are in the standby state in which their signal processing operation is stopped.
A circuit including circuit components being in such a standby state generally consumes less power than when all the circuit components of the circuit are in an operating state. Even in such a circuit, there is a leakage current flowing through the circuit components even in the standby state, and therefore power is constantly consumed.
FIG. 10 is a circuit diagram showing a standard inverter circuit as an example of a conventional transistor circuit.
The transistor circuit shown in FIG. 10 has a P-type transistor A and an N-type transistor B.
An input terminal (Input) is a portion where gates of the P-type transistor A and the N-type transistor B are connected to each other, whereas an output terminal (Output) is a portion where drains of the P-type transistor A and the N-type transistor B are connected to each other.
A supply voltage (Vdd) for the inverter circuit is supplied to a source of the P-type transistor A.
A source of the N-type transistor B is grounded.
The P-type transistor A and the N-type transistor B are short channel type transistors that have a very high signal propagation speed, but cause a leakage current (IL) at the time of non-standby operation.
Either a high potential equal to that on the Vdd side or a low potential equal to that on the ground side arrives at the input terminal (Input) as a signal. When the input terminal (Input) is at the high potential, the N-type (N channel type) transistor B is in an on state and the P-type (P channel type) transistor A is in an off state. Then, the low potential equal to that on the ground side is outputted to the output terminal (Output). On the other hand, when the input terminal (Input) is at the low potential, the P-type transistor A is in an on state and the N-type transistor B is in an off state. Then, the high potential equal to the voltage value (Vdd) is outputted to the output terminal (Output).
The leakage current (IL) in the inverter circuit shown in FIG. 10 is an unnecessary current that flows at all times through the interior of the transistors A and B connected between the Vdd side and the ground.
Since progress of LSI microfabrication techniques has lowered a withstand voltage value of a product circuit and also a supply voltage applied to the circuit, power consumption itself is on the decrease. Therefore, it may be said that a desirable environment is being formed for a product using a battery as its power supply.
On the other hand, the progress of LSI microfabrication techniques tends to increase leakage current (subthreshold current) and the like of the circuit and hence increase constant power consumption by the leakage current.
Incidentally, the input terminal (Input) in the standby state often exhibits a value intermediate between a value of the high potential and a value of the low potential, or an indefinite value.
Conventionally, in an LSI integrating transistors having a channel length of 0.35 xcexcm or more, the leakage current of the transistors is so low as to be negligible. Therefore, the amount of constant power consumption by the leakage current of the transistors in the standby state does not present much of a problem.
However, the channel length of a MOS type transistor in an LSI has recently become 0.2 xcexcm or less, and is expected to become increasingly less in the future.
Thus, it has been urgently necessary to solve the problem of constant power consumption by the leakage current.
Since the input terminal (Input) shown in FIG. 10 in the conventional LSI in the standby state often exhibits a value intermediate between a value of the high potential and a value of the low potential, or an indefinite value, an unstable through current flows through the transistors A and B in the standby state. Thus, the unstable through current also unnecessarily consumes power.
The present invention has been made in view of the above problems in the conventional transistor circuit, and it is accordingly an object of the present invention to provide a transistor circuit that can reduce unnecessary power consumption caused by the leakage current and the like during standby.
In order to solve the above problems, according to the present invention, there is provided a transistor circuit which uses a MOS transistor and stands by in a state of being supplied with a supply voltage, the transistor circuit comprising: a main circuit including one or more input terminals, one or more output terminals, one or more power supply-side terminals, and one or more MOS transistors; a P-type transistor; and an N-type transistor; wherein a supply voltage identical with the supply voltage supplied to the main circuit is applied to a source of the P-type transistor; a gate of the P-type transistor and a gate of the N-type transistor are connected to an enable terminal for on-off control of operation of the main circuit; a drain of the P-type transistor is connected to at least one output terminal of the main circuit; a drain of the N-type transistor is connected to at least one ground-side terminal of the main circuit; a source of the N-type transistor is grounded; and a channel of the N-type transistor is formed so as to be longer than a channel of the MOS transistor included in the main circuit.
Also, there is provided a transistor circuit which uses a MOS transistor and stands by in a state of being supplied with a supply voltage, the transistor circuit comprising: a main circuit including one or more input terminals, one or more output terminals, one or more power supply-side terminals, and one or more MOS transistors; a P-type transistor; and an N-type transistor; wherein the supply voltage to be supplied to the main circuit is applied to a source of the P-type transistor; a drain of the P-type transistor is connected to at least one power supply-side terminal of the main circuit; a gate of the P-type transistor and a gate of the N-type transistor are connected to an enable terminal for on-off control of operation of the main circuit; a drain of the N-type transistor is connected to at least one output terminal of the main circuit; at least one ground-side terminal of the main circuit and a source of the N-type transistor are grounded; and a channel of the P-type transistor is formed so as to be longer than a channel of the MOS transistor included in the main circuit.
In addition, there is provided a transistor circuit which uses a MOS transistor and stands by in a state of being supplied with a supply voltage, the transistor circuit comprising: one or more logical circuits having a portion where a gate of a P-type transistor and a gate of a first N-type transistor are connected to each other as an input terminal, and having a portion where a drain of the P-type transistor and a drain of the first N-type transistor are connected to each other as an output terminal, the supply voltage being applied to a source of the P-type transistor; and a second N-type transistor having a drain connected to a source of the first N-type transistor of one arbitrary logical circuit, a source connected to a ground, a gate as an enable terminal for on-off control of operation of the logical circuit, and a channel formed so as to be longer than a channel of the first N-type transistor.
In addition, there is provided a transistor circuit which uses a MOS transistor and stands by in a state of being supplied with a supply voltage, the transistor circuit comprising: one or more logical circuits having a portion where a gate of a first P-type transistor and a gate of a first N-type transistor are connected to each other as an input terminal, and having a portion where a drain of the first P-type transistor and a drain of the first N-type transistor are connected to each other as an output terminal, the supply voltage being applied to a source of the first P-type transistor; a second N-type transistor having a drain connected to a source of the first N-type transistor of one arbitrary logical circuit, a source connected to a ground, a gate as an enable terminal for on-off control of operation of the logical circuit, and a channel formed so as to be longer than a channel of the first N-type transistor; and a second P-type transistor having a source supplied with the supply voltage, a drain connected to the output terminal, and a gate connected to the enable terminal.
Moreover, there is provided a transistor circuit which uses a MOS transistor and stands by in a state of being supplied with a supply voltage, the transistor circuit comprising: one or more logical circuits having a portion where a gate of a first P-type transistor and a gate of an N-type transistor are connected to each other as an input terminal, and having a portion where a drain of the first P-type transistor and a drain of the N-type transistor are connected to each other as an output terminal, a source of the N-type transistor being grounded; and a second P-type transistor having a drain connected to a source of the first P-type transistor of one arbitrary logical circuit, a source supplied with the supply voltage, a gate as an enable terminal for on-off control of operation of the logical circuit, and a channel formed so as to be longer than a channel of the first P-type transistor.
Moreover, there is provided a transistor circuit which uses a MOS transistor and stands by in a state of being supplied with a supply voltage, the transistor circuit comprising: one or more logical circuits having a portion where a gate of a first P-type transistor and a gate of a first N-type transistor are connected to each other as an input terminal, and having a portion where a drain of the first P-type transistor and a drain of the first N-type transistor are connected to each other as an output terminal, a source of the first N-type transistor being grounded; a second P-type transistor having a drain connected to a source of the first P-type transistor of one arbitrary logical circuit, a source supplied with the supply voltage, a gate as an enable terminal for on-off control of operation of the logical circuit, and a channel formed so as to be longer than a channel of the first P-type transistor; and a second N-type transistor having a source connected to a ground, a drain connected to the output terminal, and a gate connected to the enable terminal.
Furthermore, there is provided a transistor circuit which uses a MOS transistor and stands by in a state of being supplied with a supply voltage, the transistor circuit comprising: one or more logical circuits having a portion where a gate of a first P-type transistor and a gate of a first N-type transistor are connected to each other as a first input terminal, having a portion where a gate of a second P-type transistor and a gate of a second N-type transistor are connected to each other as a second input terminal, and having a portion where a drain of the first P-type transistor, a drain of the second P-type transistor, and a drain of the first N-type transistor are connected to each other as an output terminal, the supply voltage being applied to a source of the first P-type transistor and a source of the second P-type transistor, and a source of the first N-type transistor being connected to a drain of the second N-type transistor; a third N-type transistor having a drain connected to a source of the second N-type transistor of one arbitrary logical circuit, a source connected to a ground, a gate as an enable terminal for on-off control of operation of the logical circuit, and a channel formed so as to be longer than a channel of the first N-type transistor and a channel of the second N-type transistor; and a third P-type transistor having a source supplied with the supply voltage, a drain connected to the output terminal, and a gate connected to the enable terminal.
Furthermore, there is provided a transistor circuit which uses a MOS transistor and stands by in a state of being supplied with a supply voltage, the transistor circuit comprising: one or more logical circuits having a portion where a gate of a first P-type transistor and a gate of a first N-type transistor are connected to each other as a second input terminal, having a portion where a gate of a second P-type transistor and a gate of a second N-type transistor are connected to each other as a first input terminal, and having a portion where a drain of the first N-type transistor, a drain of the second N-type transistor, and a drain of the second P-type transistor are connected to each other as an output terminal, the supply voltage being applied to a source of the first P-type transistor, a drain of the first P-type transistor being connected to a source of the second P-type transistor, and a source of the first N-type transistor being connected to a source of the second N-type transistor; a third N-type transistor having a drain connected to the source of the first N-type transistor and the source of the second N-type transistor of one arbitrary logical circuit, a source connected to a ground, a gate as an enable terminal for on-off control of operation of the logical circuit, and a channel formed so as to be longer than a channel of the first N-type transistor and a channel of the second N-type transistor; and a third P-type transistor having a source supplied with the supply voltage, a drain connected to the output terminal, and a gate connected to the enable terminal.
Thus, according to the present invention, in a transistor circuit including a logical unit using a type of MOS transistor that stands by in a state of being supplied with supply voltage, a MOS transistor for interrupting leakage current that has a channel length longer than that of the MOS transistor used in a plurality of logical circuits (more specifically, inverter circuits or the like) is placed so as to be connected in series with the logical circuits (between the supply voltage and a ground). The MOS transistor for interrupting leakage current conducts only while the transistor circuit is operated and does not conduct while the transistor circuit is in a standby state. Therefore, it is possible to reduce unnecessary power consumption by the leakage current of the logical circuits (between the supply voltage and the ground).
In addition, the transistor circuit includes a MOS transistor that does not produce effect while the transistor circuit is operated and makes the potential of an output terminal a high potential or a low potential (not intermediate potential) only while the transistor circuit is in a standby state. Therefore, it is also possible to reduce unnecessary power consumption by through-transistor current of a standby type circuit in a succeeding stage.